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PACE1757M Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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PACE1757M Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
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1 / 34 page  Document # MICRO-10 REV B Revised August 2005 PACE1757M/ME COMPLETE EMBEDDED CPU SUBSYSTEM FEATURES Implements complete MIL-STD-1750A ISA including optional MMU, MFSR, and BPU functions. Two throughput options: P1757M 2.5MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz P1757ME 3.6MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz All MIL-STD-1750A data formats and address types implemented. P1757ME includes additional matrix and vector instructions to enhance throughput in navigation, DSP transcendental and other complex alorithms. Error detection and correction and parity bit provided. Separate high drive external address & data busses. 10MHz data rate at 40MHz CPU clock System support functions included: Arbitrator for use in tightly coupled multiprocessor design. Bus control provided to aid in implementation of multi-processor systems. MIL-STD-1750A timers A & B, programmable watch dog timer and programmable bus time- out function. Start up ROM support per MIL-STD-1750A. DMA support for logical and physical memory addresses. GENERAL DESCRIPTION All functions required for a complete MIL-STD-1750A embedded CPU subsystem are in this single VLSI microcircuit occupying 1.5 square inches of board space with less than 1.9 watts of power dissipation at 40 MHz. Pyramid's P1757M/ME is a complete, single package, 3.6 MIPS subsystem solution to embedded processor requirements. The PACE 1757M uses the application-proven PACE 1750A microprocessor, the PACE 1753, and the PACE 1754. The PACE1757ME uses the enhanced PACE 1750AE microprocessor, which has additional instructions that provide high throughput for transcendental functions, navigational algorithms, and DSP functions. The PACE 1750AE is an architectural enhancement of the PACE 1750A. Programmable memory and I/O data wait state generation permits up to four different memory speeds in the same system. Programmable address wait states. Sixteen levels of interrupts are provided per MIL-STD-1750A. Interrupts can be either edge- or level-sensitive. Fault detection and handling Programmable detection of unimplemented memory or illegal I/O addresses. Full implementation of MIL-STD-1750A fault register. External address error detection. Testability and diagnostics. First falling address and data registers. Built in test - runs automatically at power on and after each reset. All hardware blocks and external busses examined. Hardware pass/fail for catastrophic failures. Status register indicates failed test. Console operating mode which allows operator to examine and change contents of registers within the CPU, any system memory location, or the I/O subsystems. Single 144-pin Quad straight lead or Gullwing 1.5 square inches of board surface. Operating temperature range -55 to +125°C; single 5V ± 10% VCC power supply; power dissipation < 1.9W (worst case at 40 MHz). |
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