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UDA1330A Datasheet(PDF) 8 Page - NXP Semiconductors |
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UDA1330A Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 24 page  2000 Apr 18 8 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS L3 INTERFACE The following system and digital sound processing features can be controlled in the L3 mode of the UDA1330ATS: • System clock frequency • Data input format • De-emphasis for 32, 44.1 and 48 kHz • Volume • Soft mute. The exchange of data and control information between the microcontroller and the UDA1330ATS is accomplished through a serial interface comprising the following signals: • L3DATA • L3MODE • L3CLOCK. Information transfer through the microcontroller bus is organized in accordance with the L3 interface format, in which two different modes of operation can be distinguished: address mode and data transfer mode. Address mode The address mode (see Fig.4) is required to select a device communicating via the L3 interface and to define the destination registers for the data transfer mode. Data bits 7 to 2 represent a 6-bit device address where bit 7 is the MSB. The address of the UDA1330ATS is 000101 (bit 7 to bit 2). If the UDA1330ATS receives a different address, it will deselect its microcontroller interface logic. Data transfer mode The selected address remains active during subsequent data transfers until the UDA1330ATS receives a new address command. The fundamental timing of data transfers (see Fig.5) is essentially the same as the address mode. The maximum input clock frequency and data rate is 64fs. Data transfer can only be in one direction, consisting of input to the UDA1330ATS to program sound processing and other functional features. All data transfers are by 8-bit bytes. Data will be stored in the UDA1330ATS after reception of a complete byte. A multibyte transfer is illustrated in Fig.6. Registers The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode using bit 1 and bit 0 (see Table 5). Table 5 Selection of data transfer The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) represent the value that is placed in the selected registers. The ‘status’ settings are given in Table 6 and the ‘data’ settings are given in Table 7. BIT 1 BIT 0 TRANSFER 0 0 data (volume, de-emphasis, mute) 0 1 not used 1 0 status (system clock frequency, data input format) 1 1 not used |
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