2K x 8 Automotive Dual-port Static RAM
CG5982AF
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-06067 Rev. *C
Revised September 6, 2005
Features
• True dual-ported memory cells that allow simultaneous
reads of the same memory location
• Automotive temperature operation: –40
°C to +115°C
• 2K x 8 organization
• High-speed access: 55 ns
• Low operating power: ICC = 120 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CG5982AF easily expands data bus width to 16
or more bits using slave
• BUSY output flag
•INT flag for port-to-port communication
Functional Description
The CG5982AF are high-speed CMOS 2K x 8 dual-port static
RAMs. Two ports are provided to permit independent access
to any location in memory. The CG5982AF can be utilized as
either a standalone 8-bit dual-port static RAM or as a MASTER
dual-port RAM in conjunction with the CG5982AF SLAVE
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. On the PLCC
version, INT is an interrupt flag indicating that data has been
placed in a unique location (7FF for the left port and 7FE for
the right port).
An automatic power-down feature is controlled independently
on each port by the chip enable (CE) pins.
The CG5982AF is available in a 52-pin PLCC package.
Notes:
1. CG5982AF (Master): BUSY is open-drain output and requires pull-up resistor.
2. Open drain outputs; pull-up resistor required.
Arbitration Logic
and
Interrupt Logic
Logic Block Diagram
Control
I/O
Control
I/O
Memory
Array
Address
Decoder
INTL
CEL
OEL
R/WL
CER
OER
R/WR
A0L
A10L
Address
Decoder
A10R
A0R
I/O7R
I/O0R
BUSYR
INTR
I/O7L
I/O0L
BUSYL
••
•
••
•
••
•
••
•
R/WL
CEL
OEL
R/WR
CER
OER
[1]
[2]
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CG5982AF 2K x 8 Automotive Dual-port Static RAM
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