1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. B SEPTEMBER 5, 2007

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

For applications not requiring the use of a differential input, both

the PCLK and nPCLK pins can be left floating. Though not

required, but for additional protection, a 1kΩ resistor can be tied

from PCLK to ground.

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

50Ω

50Ω

RTT

FOUT

FIN

RTT =

1

3.3V

125Ω

125Ω

84Ω

84Ω

FOUT

FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, ter-

minating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

designed to drive 50Ω transmission lines. Matched imped-

ance techniques should be used to maximize operating fre-

quency and minimize signal distortion. Figures 4A and 4B

show two different layouts which are recommended only as

guidelines. Other suitable clock layouts may exist and it

would be recommended that the board designers simulate

to guarantee compatibility across all printed circuit and clock

component process variations.