1998 Nov 19

4

Philips Semiconductors

Product specification

Low-voltage frequency synthesizer for

radio telephones

UMA1021AM

FUNCTIONAL DESCRIPTION

Main divider

The main divider is clocked at pin RFI by the RF signal

which is AC-coupled from an external VCO. The divider

operates with signal levels from 50 to 225 mV (RMS) and

at frequencies from 300 MHz to 2.2 GHz. It consists of a

fully programmable bipolar prescaler followed by a CMOS

counter. The main divider allows programmable ratios

from 512 to 131071 inclusive.

Reference divider

The reference divider is clocked by the signal at pin XTAL.

The applied input signal should be AC-coupled. The circuit

operates with levels from 50 up to 500 mV (RMS) and at

frequencies from 3 to 35 MHz. Any divide ratios from

8 to 2047 inclusive can be programmed.

Phase comparator and charge pump

The phase detector is driven by the edges of the output

signals of the main and reference dividers. The detector

produces current pulses at pin CP. The pulse duration is

equal to the difference in time of arrival of the edges from

the two dividers. If the main divider edge arrives first,

pin CP sinks current. If the reference divider edge arrives

first, pin CP sources current.

The current at pin CP can be controlled via the serial

programming bus as a multiple of the reference current set

by an external pull-down resistor connected between

except in the Power-down mode.

Additional circuitry is included to ensure that the gain of the

phase detector remains linear even for small phase errors.

Out-of-lock detector

The out-of-lock detector is enabled or disabled via the

serial interface by setting bit OOL (dt12) HIGH or LOW

(see Table 1). An open-drain transistor drives the output

pin LOCK. It is recommended to keep the sink current in

the LOW state below 400

µA by applying a pull-up resistor

from pin LOCK to the positive supply. When the out-of-lock

detector is enabled pin LOCK is HIGH if the error at the

phase detector input is less than approximately 25 ns,

otherwise pin LOCK is LOW. If the out-of-lock detector is

disabled, pin LOCK remains HIGH.

Serial programming bus

A simple 3-line unidirectional serial bus is used to program

the circuit.

The 3 lines are DATA (data bits), CLK (clock pulses) and

E (enable signal). The data sent to the device is loaded in

bursts framed by E. Programming clock edges and their

appropriate data bits are ignored until E goes active LOW.

The programmed information is loaded into the addressed

latch when E returns HIGH. During normal operation,

E should be kept HIGH. Only the last 21 bits serially

clocked into the device are retained within the

programming register. Additional leading bits are ignored,

and no check is made on the number of clock pulses.

The fully static CMOS design uses virtually no current

when the programming bus is inactive. It can always

capture new programmed data even during power-down.

When the synthesizer is switched on, the presence of a

signal at the reference divider input is required for correct

programming.

Data format

The data format is shown in Table 1. The first bit entered

is dt16, the last bit is ad0.

The leading bits (dt16 to dt0) make up the data field.

The four trailing bits (ad3 to ad0) are the address field.

The UMA1021AM uses 4 of the 16 available addresses.

These are chosen for compatibility with other Philips

Semiconductors radio telephone ICs. The trailing address

bits are decoded on the rising edge of E. This produces an

internal load pulse to store the data in the addressed latch.

To avoid erroneous divider ratios, the load pulse is not

allowed during data reads by the frequency dividers. This

condition is guaranteed by respecting a minimum E pulse

width after data transfer.

For the divider ratios, the first bits entered (PM16 and

PR10) are the Most Significant Bits (MSBs).

The test register (address 0000) does not normally need to

be programmed. However, if it is programmed all bits in the

data field should be set to logic 0.

Power-down mode

The synthesizer is switched on when both the power-on

input (PON) and the programmed bit dt6 (sPON) are

HIGH. When switched on, the dividers and phase detector

are synchronized to avoid random phase errors. When

switched off, the phase detector is synchronized to avoid

interrupting of the charge pump pulses.

The UMA1021AM has a very low current consumption in

the Power-down mode.