Detailed Description and

Applications Information

Figure 1 is a functional diagram of the MAX3971 limit-

ing amplifier.The signal path consists of an input buffer

followed by a gain stage and output amplifier. A feed-

back loop provides offset correction by driving the

average value of the differential output to zero.

Gain Stage and Offset Correction

The limiting amplifier provides approximately 50dB

gain. This large gain makes the amplifier susceptible to

small DC offsets, which cause deterministic

jitter. A low-frequency loop is integrated into the limiting

amplifier to reduce output offset, typically to less than

2mV.

The external capacitor CZ is required to set the low-fre-

quency cutoff for the offset correction loop and for sta-

bility. The time constant of the loop is set by the

product of an equivalent 20k

Ω on-chip resistor and the

value of the off-chip capacitor, CZ. For stable opera-

tion, the minimum value of CZ is 0.01µF. To minimize

pattern-dependent jitter, CZ should be as large as pos-

sible. For 10-Gigabit Ethernet applications, the typical

value of CZ is 0.1µF. Keep CZ as close to the package

as possible.

CML Input Circuit

The input buffer is designed to accept CML input sig-

nals such as the output from the MAX3970 transimped-

ance amplifier. An equivalent circuit for the input is

shown in Figure 2. DC-coupling the inputs is not recom-

mended because doing so prevents the part’s offset

correction circuitry from working properly. Thus, AC-

coupling capacitors are required on the input.

CML Output Circuit

An equivalent circuit for the output network is shown in

Figure 3. It consists of two 50

Ω resistors connected to

transistor pair (Q1 and Q2). The differential output sig-

nals are clamped by transistors Q3 and Q4 when the

DISABLE input is high.

Disable Function

A logic signal can be applied to the DISABLE pin to

squelch the output signal. When the output is disabled,

an offset is added to the output, preventing the follow-

ing stage from oscillating (if DC-coupled).

+3.3V, 10.3Gbps Limiting Amplifier

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5

MAX3971

CZ-

CZ+

LOWPASS

FILTER

CZ

OFFSET

CORRECTION

AMP

INPUT

AMPLIFIER

GAIN

50dB

OUTPUT

AMPLIFIER

OUT+

OUT-

IN+

GNDIN+

GNDIN-

IN-

DISABLE

Figure 1. Functional Diagram

50

Ω

50

Ω

IN+

GNDIN+

GNDIN-

IN-

ESD

STRUCTURES

Figure 2. CML Input Equivalent Circuit

50

Ω

50

Ω

Q1

Q2

Q3

Q4

OUT+

OUT-

DISABLE

DATA

ESD

STRUCTURES

Figure 3. CML Input Equivalent Circuit Showing Clamping

Circuit for Squelching the Output Signal