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ICS873991-147 Datasheet(PDF) 1 Page - Integrated Device Technology |
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ICS873991-147 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 17 page LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR ICS873991-147 IDT™ / ICS™ LVPECL/ECL CLOCK GENERATOR 1 ICS873991AY-147 REV. A AUGUST 10, 2007 PRELIMINARY GENERAL DESCRIPTION The ICS873991-147 is a low voltage, low skew, 3.3V LVPECL or ECL Clock Generator and a member of the HiPerClock S ™ family of High Performance Clock Solutions from IDT. The ICS873991-147 has two selectable clock inputs. The PCLK, nPCLK pair can accept an LVPECL input and the REF_CLK pin can accept a LVCMOS or LVTTL input. This device has a fully integrated PLL along with frequency configurable outputs. An external feedback input and output regenerates clocks with “zero de- lay”. The four independent banks of outputs each have their own output dividers, which allow the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The output frequency range is 25MHz to 500MHz and the input frequency range is 6.25MHz to 125MHz. The PLL_SEL input can be used to bypass the PLL for test and system debug purposes. In bypass mode, the input clock is routed around the PLL and into the internal output dividers. The ICS873991-147 also has a SYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs for coincident rising edges and signals a pulse per the timing diagrams in this data sheet. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of each other. Example Applications: 1. Line Card Multiplier: Multiply 19.44MHz from a back-plane to 77.76MHz on the line card ASIC and Serdes. 2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies from a reference clock to multiple processing units on an embedded system. HiPerClockS™ ICS FEATURES • Fourteen differential 3.3V LVPECL/ECL outputs • Selectable differential LVPECL or REF_CLK inputs • PCLK, nPCLK can accept the following input levels: LVPECL, CML, SSTL • REF_CLK accepts the following input levels: LVCMOS, LVTTL • Input clock frequency range: 6.25MHz to 125MHz • Maximum output frequency: 500MHz • VCO range: 200MHz to 1GHz • Output skew: 70ps (typical) • Cycle-to-cyle jitter: 35ps (typical) • LVPECL mode operating voltage supply range: V CC = 3.135V to 3.465V, VEE = 0V • ECL mode operating voltage supply range: V CC = 0V, VEE = -3.465V to -3.135V • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) package • Industrial temperature available upon request PIN ASSIGNMENT nQB3 QB3 VCCO nQA0 QA0 nQA1 QA1 nQA2 QA2 nQA3 QA3 SYNC_SEL VCO_SEL 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 20 19 18 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 28 27 QC1 nQC1 QC0 nQC0 VCCO QD1 nQD1 QD0 nQD0 VCCO QFB nQFB VCCA ICS873991-147 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. |
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