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ICS9FG108 Datasheet(PDF) 9 Page - Integrated Device Technology |
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ICS9FG108 Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 19 page  IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG108 REV G 04/06/07 ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 9 SMBus Table: PLL Frequency Control Register Pin # Name Control Function Type0 1 PWD Bit 7 PLL N Div8 N Divider Prog bit 8 RW X Bit 6 PLL N Div9 N Divider Prog bit 9 RW X Bit 5 PLL M Div5 RW X Bit 4 PLL M Div4 RW X Bit 3 PLL M Div3 RW X Bit 2 PLL M Div2 RW X Bit 1 PLL M Div1 RW X Bit 0 PLL M Div0 RW X SMBus Table: PLL Frequency Control Register Pin # Name Control Function Type0 1 PWD Bit 7 PLL N Div7 RW X Bit 6 PLL N Div6 RW X Bit 5 PLL N Div5 RW X Bit 4 PLL N Div4 RW X Bit 3 PLL N Div3 RW X Bit 2 PLL N Div2 RW X Bit 1 PLL N Div1 RW X Bit 0 PLL N Div0 RW X SMBus Table: PLL Spread Spectrum Control Register Pin # Name Control Function Type0 1 PWD Bit 7 PLL SSP7 RW X Bit 6 PLL SSP6 RW X Bit 5 PLL SSP5 RW X Bit 4 PLL SSP4 RW X Bit 3 PLL SSP3 RW X Bit 2 PLL SSP2 RW X Bit 1 PLL SSP1 RW X Bit 0 PLL SSP0 RW X SMBus Table: PLL Spread Spectrum Control Register Pin # Name Control Function Type0 1 PWD Bit 7 0 Bit 6 PLL SSP14 RW X Bit 5 PLL SSP13 RW X Bit 4 PLL SSP12 RW X Bit 3 PLL SSP11 RW X Bit 2 PLL SSP10 RW X Bit 1 PLL SSP9 RW X Bit 0 PLL SSP8 RW X - - Spread Spectrum Programming bit(14:8) These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL - - - - Byte 13 - Reserved - - - Spread Spectrum Programming bit(7:0) These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL - - - - Byte 12 - - N Divider Programming Byte11 bit(7:0) and Byte10 bit(7:6) The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] - - - - - - - - - Byte 11 - Byte 10 - The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] - - M Divider Programming bit (5:0) - - - |
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