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ICS9DB801C Datasheet(PDF) 3 Page - Integrated Device Technology |
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ICS9DB801C Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 19 page IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz) ICS9DB801C REV C 08/16/07 ICS9DB801C Eight Output Differential Buffer for PCI Express (50-200MHz) 3 Pin Description for OE_INV = 0 PIN # PIN NAME PIN TYPE DESCRIPTION 1 SRC_DIV# INPUT Active low Input for determining SRC output frequency SRC or SRC/2. 0 = SRC/2, 1= SRC 2 VDD POWER Power supply, nominal 3.3V 3 GND POWER Ground pin. 4 SRC_IN INPUT 0.7 V Differential SRC TRUE input 5 SRC_IN# INPUT 0.7 V Differential SRC COMPLEMENTARY input 6 OE_0 INPUT Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 7 OE_3 INPUT Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 8 DIF_0 OUTPUT 0.7V differential true clock outputs 9 DIF_0# OUTPUT 0.7V differential complement clock outputs 10 GND POWER Ground pin. 11 VDD POWER Power supply, nominal 3.3V 12 DIF_1 OUTPUT 0.7V differential true clock outputs 13 DIF_1# OUTPUT 0.7V differential complement clock outputs 14 OE_1 INPUT Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 15 OE_2 INPUT Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 16 DIF_2 OUTPUT 0.7V differential true clock outputs 17 DIF_2# OUTPUT 0.7V differential complement clock outputs 18 GND POWER Ground pin. 19 VDD POWER Power supply, nominal 3.3V 20 DIF_3 OUTPUT 0.7V differential true clock outputs 21 DIF_3# OUTPUT 0.7V differential complement clock outputs 22 BYPASS#/PLL INPUT Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode 23 SCLK INPUT Clock pin of SMBus circuitry, 5V tolerant. 24 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. |
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