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July 19, 2007

IDT 89HPES32H8 Data Sheet

– Supports optional PCI Express end-to-end CRC checking

– Supports optional PCI Express Advanced Error Reporting

– Supports PCI Express Hot-Plug

• Compatible with Hot-Plug I/O expanders used on PC

motherboards

– Supports Hot-Swap

◆

Power Management

– Supports PCI Power Management Interface specification,

Revision 1.1 (PCI-PM)

• Supports powerdown modes at the link level (L0, L0s, L1,

– Unused SerDes disabled

◆

Testability and Debug Features

– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator

– Ability to read and write any internal register via the SMBus

– Ability to bypass link training and force any link into any mode

– Provides statistics and performance counters

◆

Thirty-two General Purpose Input/Output pins

– Each pin may be individually configured as an input or output

– Each pin may be individually configured as an interrupt input

– Some pins have selectable alternate functions

◆

Packaged in a 31mm x 31mm 900-ball Flip Chip BGA with

1mm ball spacing

Product Description

Utilizing standard PCI Express interconnect, the PES32H8 provides

the most efficient system interconnect switching solution for applications

requiring maximum throughput, low latency, and simple board layout

with a minimum number of board layers. It provides 128 Gbps of aggre-

gated, full-duplex switching capacity through 32 integrated serial lanes,

using proven and robust IDT technology. Each lane provides 2.5 Gbps

of bandwidth in both directions and is fully compliant with PCI Express

Base specification 1.1.

The PES32H8 is based on a flexible and efficient layered architec-

ture. The PCI Express layer consists of SerDes, Physical, Data Link and

Transaction layers in compliance with PCI Express Base specification

Revision 1.1. The PES32H8 can operate either as a store and forward

or cut-through switch and is designed to switch memory and I/O transac-

tions. It supports eight Traffic Classes (TCs) and two Virtual Channels

(VC) with sophisticated resource management to enable efficient

switching and I/O connectivity for servers, storage, and embedded appli-

cations.

SMBus Interface

The PES32H8 contains two SMBus interfaces. The slave interface

provides full access to the configuration registers in the PES32H8,

allowing every configuration register in the device to be read or written

by an external agent. The master interface allows the default configura-

tion register values of the PES32H8 to be overridden following a reset

with values programmed in an external serial EEPROM. The master

interface is also used by an external Hot-Plug I/O expander.

Six pins make up each of the two SMBus interfaces. These pins

consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus

address pins. In the slave interface, these address pins allow the SMBus

address to which the device responds to be configured. In the master

interface, these address pins allow the SMBus address of the serial

configuration EEPROM from which data is loaded to be configured. The

SMBus address is set up on negation of PERSTN by sampling the

corresponding address pins. When the pins are sampled, the resulting

address is assigned as shown in Table 1.

Figure 2 Port Configuration Examples

Note: The configurations in the above diagram show the maximum port widths. The PES32H8 can negotiate to narrower port widths — x4,

x2, or x1.

x8

x8

1 0

2

3

Non-bifurcated

Fully Bifurcated

x8

4 5

x8

7

6

2

3

4

5

6

7

x4

x4

0

x4

1

x4

x4

x4

x4

x4