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AD9920A Datasheet(PDF) 1 Page - Analog Devices |
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AD9920A Datasheet(HTML) 1 Page - Analog Devices |
1 / 2 page 12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator AD9920A Rev. Sp0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. FEATURES Integrated 19-channel V-driver 1.8 V AFETG core 24 programmable vertical clock signals Correlated double sampler (CDS) with −3 dB, 0 dB, +3 dB, and +6 dB gain 12-bit, 40.5 MHz analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing generator Precision Timing core with ~400 ps resolution On-chip 3 V horizontal and RG drivers General-purpose outputs (GPOs) for shutter and system support On-chip sync generator with external sync input On-chip 1.8 V low dropout (LDO) 105-lead 8 mm × 8 mm CSP_BGA package APPLICATIONS Digital still cameras GENERAL DESCRIPTION The AD9920A is a highly integrated charge-coupled device (CCD) signal processor for digital still camera applications. It includes a complete analog front end (AFE) with analog-to-digital conversion, combined with a full-function programmable timing generator and 19-channel vertical driver (V-driver). The timing generator is capable of supporting up to 26 vertical clock signals to control advanced CCDs. The on-chip V-driver supports up to 19 channels for use with 6-field CCDs. A Precision Timing™ core allows adjust- ment of high speed clocks with approximately 400 ps resolution at 40.5 MHz operation. The AD9920A also contains six GPOs that can be used for shutter and system functions. The analog front end includes black level clamping, variable gain CDS, and a 12-bit ADC. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. The AD9920A is specified over an operating temperature range of −25°C to +85°C. FUNCTIONAL BLOCK DIAGRAM AD9920A CDS VGA CLAMP 12-BIT ADC DCLK SCK SDATA CLI VREF 6dB TO 42dB HORIZONTAL DRIVERS VERTICAL TIMING CONTROL RG H1 TO H8 24 GPO5 GPO6 REFT REFB PRECISION TIMING GENERATOR SYNC GENERATOR INTERNAL CLOCKS HD VD INTERNAL REGISTERS CCDIN –3dB, 0dB, +3dB, +6dB 12 HL CLO GPO1 TO GPO4, GPO7, GPO8 XV1 TO XV24 XSUBCK 8 6 1.8V OUTPUT 3V INPUT LDO REG VERTICAL DRIVER 19 SUBCK XSUBCNT SYNC/RSTB V1A TO V6 (3-LEVEL) V7 TO V15 (2-LEVEL) DOUT SL Figure 1. For more information about the AD9920A, contact Analog Devices via email at afe.ccd@analog.com. |
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