M65KG512AB datasheet(1/54 Pages) STMICROELECTRONICS

Part #	M65KG512AB

Description	512Mbit (4 banks x 8 Mb x 16) 1.8 V supply, DDR low power SDRAM

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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1 / 54 page

February 2007

Rev 3

1/54

1

M65KG512AB

512Mbit (4 banks x 8 Mb x 16)

1.8 V supply, DDR low power SDRAM

Features

■

512Mbit Synchronous Dynamic RAM

– Organized as 4 banks of 8 Mwords, each

16 bits wide

■

Double Data Rate (DDR)

– 2 Data Transfers/Clock cycle

– Data Rate: 332 Mbit/s max. for 6ns speed

class

■

Supply voltage

–VDD = 1.7 to 1.9 V (1.8 V typical in

accordance with JEDEC standard)

–VDDQ = 1.7 to 1.9 V for Inputs/Outputs

■

Synchronous Burst Read and Write

– Fixed Burst Lengths: 2-, 4-, 8-, 16 words

– Burst Types: Sequential and Interleaved.

– Clock Frequency: 133 MHz (7.5 ns speed

class), 166 MHz (6 ns speed class)

– Clock Valid to Output Delay (CAS Latency):

3 at the maximum clock frequency

– Burst Read Control by Burst Read

Terminate And Precharge Commands

■

Automatic Precharge

■

Byte Write controlled by LDQM and UDQM

■

Low-power features

– Partial Array Self Refresh (PASR)

– Automatic Temperature Compensated Self

Refresh (ATCSR)

– Driver Strength (DS)

– Deep Power-Down mode

– Auto Refresh and Self Refresh

■

LVCMOS interface compatible with multiplexed

addressing

■

Operating temperature:

–

−30 to 85 °C

–

−30 to 105 °C

The M65KG512AB is only available as part of a multi-chip package product.

Wafer

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