CY7B9911
RoboClock+™
Document Number: 38-07209 Rev. *B
Page 11 of 13
Figure 7 shows some of the functions that are selectable on the
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output allows the system designer to clock different subsystems
on opposite edges, without suffering from the pulse asymmetry
typical of non-ideal loading. This function enables each of the
two subsystems to clock 180 degrees out of phase, but still stay
aligned within the skew specification.
The divided outputs offer a zero delay divider for portions of the
system that divides the clock by either two or four, and still remain
within a narrow skew of the “1X” clock. Without this feature,
addition of an external divider is required and the propagation
delay of the divider adds to the skew between the different clock
signals.
These divided outputs, coupled with the Phase Locked Loop,
enable the PSCB to multiply the clock rate at the REF input by
either two or four. This mode enables the designer to distribute
a low frequency clock between various portions of the system. It
also locally multiplies the clock rate to a more suitable frequency,
maintaining the low skew characteristics of the clock driver. The
PSCB performs all of the functions described in this section at
the same time. It can multiply by two and four or divide by two
(and four) at the same time that it is shifting its outputs over a
wide range or maintaining zero skew between selected outputs.
Figure 8. Multi-Function Clock Driver
Figure 9. Board-to-Board Clock Distribution
20 MHz
DISTRIBUTION
CLOCK
80 MHz
INVERTED
Z0
20 MHz
80 MHz
ZEROSKEW
80 MHz
SKEWED4ns
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
LOAD
LOAD
LOAD
LOAD
Z0
Z0
Z0
SYSTEM
CLOCK
Z0
L1
L2
L3
L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
FS
FB
LOAD
LOAD
LOAD
LOAD
LOAD
TEST
Z0
Z0
Z0