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IDT70P3337S250RM Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT70P3337S250RM Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 20 page 18/9Mb QDR-IITM x18 IDT70P3307/70P3337 SYNCHRONOUS Dual QDR-IITM Preliminary Datasheet Commercial Temperatue Range 7 July 16, 2007 Device Selected EP[0] EP[1] E[0] E[1] Bank 0 VSS VSS LL Bank 1 VDD VSS HL Bank 2 VSS VDD LH Bank 3 VDD VDD HH 6725 tbl05 Truth Table III - Port Enable Pins(1) Normal Read and Writes NOTES: 1. EP [1:0] - Port Enable Programming Polarity (see pin description for the entire device). 2. Ex[1:0] - Port Enable (see pin description assigned for each port). Cascade/Multi-Drop using Port Enable (E0 & E1) Pins As shown below in Figure 1 four devices can be cascaded using the Port Enable (E0,E1) pins scheme. The port enable pins are subject to the same DC characteristics as the QDR interface. Refer to Pin Definitions table for pin descriptions. This diagram illustrates one port of a QDR-II dual port Figure 1. Multi-drop Cascading using the Chip Enable E[1:0] Pins |
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