IDT74SSTUBH32865A

28-BIT 1:2 REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

28-BIT 1:2 REGISTERED BUFFER FOR DDR2

6

IDT74SSTUBH32865A

7103/10

Parity and Standby Function Table

Outputs

RESET

DCS0

DCS1

CLK

CLK

Σ of Inputs = H (D1 - D21)

HL

X

↑↓

Even

L

H

HL

X

↑↓

Odd

L

L

HL

X

↑↓

Even

H

L

HL

X

↑↓

Odd

H

H

HX

L

↑↓

Even

L

H

HX

L

↑↓

Odd

L

L

HX

L

↑↓

Even

H

L

HX

L

↑↓

Odd

H

H

HH

H

↑↓

X

X

H

X

X

L or H

L or H

X

X

LX or

Floating

X or

Floating

X or

Floating

X or

Floating

X or Floating

X or Floating

H

1

H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

↑ = LOW to HIGH

↓ = HIGH to LOW

2

PARIN arrives one clock cycle after the data to which it applies.

3

This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If

PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.