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CY7B9940V-5AC Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7B9940V-5AC
Description  High-Speed Multi-Frequency PLL Clock Buffer
Download  9 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7B9940V-5AC Datasheet(HTML) 5 Page - Cypress Semiconductor

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RoboClockII™ Junior
CY7B9930V
CY7B9940V
Document #: 38-07271 Rev. *B
Page 5 of 9
Operating Current
ICCI
Internal Operating
Current
CY7B9930V
VCC = Max., fMAX
[5]
–200
mA
CY7B9940V
200
mA
ICCN
Output Current
Dissipation/Pair[6]
CY7B9930V
VCC = Max.,
CLOAD = 25 pF,
RLOAD = 50Ω at VCC/2,
fMAX
–40
mA
CY7B9940V
50
mA
Capacitance
Parameter
Description
Test Conditions
Min.
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
5
pF
Switching Characteristics Over the Operating Range[7, 8, 9, 10, 11]
Parameter
Description
CY7B9930/40V-2
CY7B9930/40V-5
Unit
Min.
Max.
Min.
Max.
fin
Clock Input Frequency
CY7B9930V
12
100
12
100
MHz
CY7B9940V
24
200
24
200
MHz
fout
Clock Output Frequency
CY7B9930V
12
100
12
100
MHz
CY7B9940V
24
200
24
200
MHz
tSKEWPR
Matched-Pair Skew[12, 13]
–185–185
ps
tSKEWBNK
Intrabank Skew[12, 13]
–200–250
ps
tSKEW0
Output-Output Skew (same frequency and phase, rise to rise, fall
to fall)[12, 13]
–250–550
ps
tSKEW1
Output-Output Skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall)[12, 13]
–250–650
ps
tCCJ1-3
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
–150–150
ps
Peak-
Peak
tCCJ4-12
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
–100–100
ps
Peak-
Peak
tPD
Propagation Delay, REF to FB Rise
–250
250
–500
500
ps
tPDDELTA
Propagation Delay difference between two devices[14]
–200
200
ps
tREFpwh
REF input (Pulse Width HIGH)[15]
2.0
2.0
ns
tREFpwl
REF input (Pulse Width LOW)[15]
2.0
2.0
ns
tr/tf
Output Rise/Fall Time[16]
0.15
2.0
0.15
2.0
ns
tLOCK
PLL Lock Time From Power-up
10
10
ms
tRELOCK1
PLL Re-Lock Time (from same frequency, different phase) with
Stable Power Supply
–500–500
µs
Notes:
5.
ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B9930V, fNOM = 200 MHz for
CY7B9940V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
6.
This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum
load of 25 pF terminated to 50
Ω at V
CC/2.
7.
This is for non-three level inputs.
8.
Assumes 25 pF Max. Load Capacitance up to 185 Mhz. At 200 MHz the max load is 10 pF.
9.
Both outputs of pair must be terminated, even if only one is being used.
10. Each package must be properly decoupled.
11.
AC parameters are measured at 1.5V, unless otherwise indicated.
12. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when
all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
15. Tested initially and after any design or process changes that may affect these parameters.
16. Rise and fall times are measured between 2.0V and 0.8V.
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
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