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RC32365T365-150BCI Datasheet(PDF) 11 Page - Integrated Device Technology |
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RC32365T365-150BCI Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 44 page 11 of 44 October 5, 2005 RC32365 Boot Configuration Vector The boot configuration vector is read into the RC32365 during cold reset. The vector defines parameters in the RC32365 that are essential to oper- ation when cold reset is complete. The encoding of boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. Signal Name/Description MDATA[2:0] CPU Clock Multiplier. This field specifies the value by which the PLL multiplies the master clock input (CLK) to obtain the processor clock frequency (PCLK). 0x0 - Multiply by 2 0x1 - 0x7 — Reserved MDATA[3] Endian. This bit specifies the endianness. 0x0 - little endian 0x1 - big endian MDATA[4] Reserved. This pin may be driven high or low during boot configuration and its state is recorded in the Boot Configuration Vector (BCV) field of the BCV register. This reserved bit may be used to pass boot configuration parameters to software. MDATA[6:5] Boot Device Width. This field specifies the width of the boot device (i.e., Device 0). 0x0 - 8-bit boot device width 0x1 - 16-bit boot device width 0x2 - 32-bit boot device width 0x3 - reserved MDATA[7] Reset Mode. This bit specifies the length of time the RSTN signal is driven. 0x0 - Normal reset: RSTN driven for minimum of 4096 clock cycles 0x1 - reserved MDATA[8] Disable Watchdog Timer. When this bit is set, the watchdog timer is disabled following a cold reset. 0x0 - Watchdog timer is enabled 0x1 - Watchdog timer is disabled MDATA[11:9] PCI Mode. This bit controls the operating mode of the PCI bus interface. The initial value of the EN bit in the PCIC register is determined by the PCI mode. 0x0 - Disabled (EN initial value is zero) 0x1 - PCI satellite mode with PCI target not ready (EN initial value is one) 0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one) 0x3 - PCI host mode with external arbiter (EN initial value is zero) 0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm (EN initial value is zero) 0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm (EN initial value is zero) 0x6 - reserved 0x7 - reserved MDATA[15:12] Reserved. These pins may be driven high or low during boot configuration and their state is recorded in the Boot Configuration Vector (BCV) field of the BCV register. These reserved bits may be used to pass boot configuration parameters to software. Table 3 Boot Configuration Vector Encoding |
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