PRELIMINARY
CY7B9945V
Document Number: 38-07336 Rev. *F
Page 8 of 11
Capacitance
Parameter
Description
Test Conditions
Min
Max
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
–
5
pF
Switching Characteristics
Over the Operating Range [5, 7, 8, 9, 10]
Parameter
Description
CY7B9945V-2 CY7B9945V-5
Unit
Min
Max
Min
Max
fin
Clock Input Frequency
24
200
24
200
MHz
fout
Clock Output Frequency
24
200
24
200
MHz
tSKEWPR
Matched Pair Skew[12, 13],1Q[0:1],1Q[2:3],2Q[0:1],2Q[2:3],2Q[4:5]
–
200
–
200
ps
tSKEWBNK
Intrabank Skew[12, 13]
–250–250
ps
tSKEW0
Output-Output Skew (same frequency and phase, rise to rise, fall to fall)[12, 13]
–250–550
ps
tSKEW1
Output-Output Skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall)[12, 13]
–250–650
ps
tSKEW2
Output-Output Skew (all output configurations outside of tSKEW0 and
tSKEW1)
[10, 11]
–500–800
ps
tCCJ1-3
Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3)
–
150
–
150
ps
Peak-
Peak
tCCJ4-12
Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5,
6, 8, 10, 12)
–100–100
ps
Peak-
Peak
tPD
Propagation Delay, REF to FB Rise
–250
250
–500
500
ps
TTB
Total Timing Budget window (same frequency and phase)[14, 15]
–500–700
ps
tPDDELTA
Propagation Delay difference between two devices[16]
–200–200
ps
tREFpwh
REF input (Pulse Width HIGH)[5]
2.0
–
2.0
–
ns
tREFpwl
REF input (Pulse Width LOW)[5]
2.0
–
2.0
–
ns
tr/tf
Output Rise/Fall Time[17]
0.15
2.0
0.15
2.0
ns
tLOCK
PLL Lock TIme From Power Up
–
10
–
10
ms
tRELOCK1
PLL Relock Time (from same frequency, different phase) with Stable
Power Supply
–500–500
μs
tRELOCK2
PLL Re-lock Time (from different frequency, different phase) with Stable
Power Supply[16]
–1000
–1000
μs
tODCV
Output duty cycle deviation from 50%[11]
–1.0
1.0
–1.0
1.0
ns
tPWH
Output HIGH time deviation from 50%[19]
–1.5–1.5
ns
tPWL
Output LOW time deviation from 50%[19]
–2.0–2.0
ns
tPDEV
Period deviation when changing from reference to reference[20]
–
0.025
–
0.025
UI
tOAZ
DIS[1:2] HIGH to output high-impedance from ACTIVE[12, 21]
1.0101.0
10
ns
tOZA
DIS[1:2] LOW to output ACTIVE from output is high impedance[21, 22]
0.5140.5
14
ns
Notes
6. Assumes 25 pF Maximum Load Capacitance up to 185 MHz. At 200 MHz the maximum load is 10 pF.
7. Both outputs of pair must be terminated, even if only one is being used.
8. Each package must be properly decoupled.
9. AC parameters are measured at 1.5V, unless otherwise indicated.
10. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω up to185 MHz and 10 pF load to 200 MHz.
11. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase dellay has been selected when
all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
12. Tested initially and after any design or process changes that affect these parameters.
13. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew,
cycle-cycle jitter, and dynamic phase error. TTB is equal to or smaller than the maximum specified value at a given output frequency.
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