2K x 8 Static RAM
CY7C128A
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05028 Rev. *A
Revised August 3, 2006
Features
• Automatic power-down when deselected
• CMOS for optimum speed/power
•High speed
—15 ns
• Low active power
— 660 mW (commercial)
• Low standby power
— 110 mW (20 ns)
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electro-
static discharge
• Available in Pb-free and non Pb-free 24-pin Molded
SOJ, non Pb-free 24-pin (300-Mil) Molded DIP
Functional Description
The CY7C128A is a high-performance CMOS static RAM
organized as 2048 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), and active
LOW Output Enable (OE) and tri-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O0 through I/O7) is written into the
memory location specified on the address pins (A0 through
A10).
Reading the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while Write Enable (WE)
remains HIGH. Under these conditions, the contents of the
memory location specified on the address pins will appear on
the eight I/O pins.
The I/O pins remain in high-impedance state when Chip
Enable (CE) or Output Enable (OE) is HIGH or Write Enable
(WE) is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
Logic Block Diagram
Pin Configurations
C128A–1
A1
A2
A4
A5
A6
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
12
13
A6
A5
A4
A3
WE
VCC
A8
A9
A10
I/O5
I/O4
I/O3
C128A–2
A7
I/O0
I/O1
CE
OE
128 x 16 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
7C128A
A0
A3
A7
A8
A9
A10
I/O2
GND
I/O7
I/O6
A2
A1
A0
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