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CY7C185
Document #: 38-05043 Rev. *B
Page 4 of 12
Switching Waveforms
Read Cycle No.1[8,9]
Read Cycle No.2[10,11]
Notes:
8. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
9. WE is HIGH for read cycle.
10. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL.
11. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH
to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
HIGH
DATA OUT
VCC
SUPPLY
CURRENT
CE1
OE
CE2
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