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CY7C199CN
Document #: 001-06435 Rev. *B
Page 8 of 14
Write Cycle 1 (WE controlled) [13, 14, 15]
Write Cycle 2 (CE controlled) [14, 16, 17]
Timing Waveforms (continued)
Address
CE
WE
Data In/Out
t
WC
Data-In Valid
t
SCE
t
SA
t
AW
t
PWE
t
HA
t
HD
t
SD
OE
t
HZOE
Undefined
see footnotes
Address
CE
WE
Data In/Out
t
WC
Data-In Valid
t
SCE
t
SA
t
AW
t
HA
t
HD
t
SD
High Z
High Z
Notes
13. This cycle is WE controlled, OE is HIGH during write.
14. Data in and/or out is high impedance if OE = VIH.
15. During this period the IOs are in output state and input signals must not be applied.
16. This cycle is CE controlled.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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