2 / 3 page
CY7C637xx
2
When a rising edge interrupt is enabled for a GPIO pin, reading the GPIO Port 1 coincident to a falling edge
of that GPIO signal may generated a false GPIO intterupt
• PARAMETERS AFFECTED
Interrupts
• TRIGGER CONDITION(S)
Reading the GPIO Port 1 when either rising or falling edge interrupts are enabled for a GPIO pin.
• SCOPE OF IMPACT
The chip enters the GPIO Interrupt Service Routine (ISR) in error.
• WORKAROUND
Workarounds will need to be tailored to individual applications based on the flexibility of changing the GPIO
usage, the timing of the GPIO interrupt sources and firmware interrupt latencies.
• FIX STATUS
No silicon fix is planned.
References
1. 38-08022 CY7C63722/23/43 enCoRe™ USB Combination Low-speed USB & PS/2 Peripheral Controller
datasheet.
Note 1: Port 1 Read is an internal signal that is asserted when Port 1
is read with an "IORD 01h" instruction.
Note 2: The GPIO Interrupt signal is an internal signal. The arrow
indicates that a GPIO interrupt is triggered.
Any Port 0 or Port 1 GPIO
pin with Rising Edge GPIO
Interrupt Enabled
Port 1 Read Signal
(See Note 1)
GPIO Interrupt Signal
(See Note 2)
Proper GPIO
Interrupt Trigger
False GPIO interrupt
on a Falling edge
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
