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CY7C1011CV33
Document #: 38-05232 Rev. *E
Page 6 of 11
Read Cycle No. 2 (OE Controlled)[11, 12]
Write Cycle No. 1 (CE Controlled)[13, 14]
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE, BLE
CURRENT
ICC
ISB
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATAI/O
ADDRESS
CE
WE
BHE, BLE
t
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