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CY7C1011DV33
Document #: 38-05609 Rev. *C
Page 5 of 11
tDBE
Byte Enable to Data Valid
5
ns
tLZBE
Byte Enable to Low-Z
0
ns
tHZBE
Byte Disable to High-Z
6
ns
Write Cycle[9, 10]
tWC
Write Cycle Time
10
ns
tSCE
CE LOW to Write End
7
ns
tAW
Address Set-up to Write End
7
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
7
ns
tSD
Data Set-up to Write End
5
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low-Z[8]
3ns
tHZWE
WE LOW to High-Z[7, 8]
5ns
tBW
Byte Enable to End of Write
7
ns
Data Retention Characteristics Over the Operating Range
Parameter
Description
Conditions[12]
Min.
Max.
Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
Data Retention Current
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
10
mA
tCDR
[3]
Chip Deselect to Data Retention
Time
0ns
tR
[13]
Operation Recovery Time
tRC
ns
Data Retention Waveform
AC Switching Characteristics Over the Operating Range[5] (continued)
Parameter
Description
–10
Unit
Min.
Max.
3.0V
3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
Notes
9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
10. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
12. No input may exceed VCC + 0.3V.
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs
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