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P4C150-15CM Datasheet(PDF) 3 Page - Pyramid Semiconductor Corporation |
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P4C150-15CM Datasheet(HTML) 3 Page - Pyramid Semiconductor Corporation |
3 / 11 page P4C150 Page 3 of 11 Document # SRAM105 REV A Notes: 5.WE is HIGH for READ cycle. 6.CS and OE are LOW for READ cycle. 7.ADDRESS must be valid prior to, or concident with, CS transition LOW, t AA must still be met. Min Sym. t RC t AA t AC t HZ t OE t OLZ Read Cycle Time Chip Select Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Data Valid Output Enable to Output in Low Z -10 -12 -15 -20 -25 -35 Unit ns ns ns ns ns ns ns ns Min Max 10 8 4 10 2 2 AC CHARACTERISTICS—READ CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) 12 2 2 Max 12 10 6 Min 15 2 2 Max 15 12 8 Min 20 2 2 Max 20 14 10 Min 25 2 2 Max 25 15 13 Min 35 2 2 Max 35 35 15 Parameter Address Access Time t OH t LZ t OHZ Output Disable to Output in High Z 7 9 10 14 15 20 22 2 2 2 2 57 9 11 13 16 ns TIMING WAVEFORM OF READ CYCLE NO. 1(5,6) 8. Transition is measured ±200 mV from steady state voltage prior to change, with loading as specified in Figure 1. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. TIMING WAVEFORM OF READ CYCLE NO. 2 (CS CS CS CS CS CONTROLLED)(5,7) |
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