CY7C1019B

Document #: 38-05026 Rev. *C

Page 3 of 8

Parameter

Description

-12

-15

Unit

Min.

Max.

Min.

Max.

Read Cycle

Read Cycle Time

12

15

ns

Address to Data Valid

12

15

ns

Data Hold from Address Change

3

3

ns

CE LOW to Data Valid

12

15

ns

OE LOW to Data Valid

6

7

ns

OE LOW to Low Z

0

0

ns

OE HIGH to High Z

[5, 6]

67

ns

CE LOW to Low Z

[6]

33

ns

CE HIGH to High Z

[5, 6]

67

ns

CE LOW to Power-Up

0

0

ns

CE HIGH to Power-Down

12

15

ns

Write Cycle Time

12

15

ns

CE LOW to Write End

9

10

ns

Address Set-Up to Write End

8

10

ns

Address Hold from Write End

0

0

ns

Address Set-Up to Write Start

0

0

ns

WE Pulse Width

8

10

ns

Data Set-Up to Write End

6

8

ns

Data Hold from Write End

0

0

ns

WE HIGH to Low Z

[6]

33

ns

WE LOW to High Z

[5, 6]

67

ns

Notes:

4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any

of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.