6

COMMERCIALTEMPERATURERANGE

IDTCSPU877D

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

TIMING REQUIREMENTS

Symbol

Parameter

Min.

Max.

Unit

125

340

MHz

160

340

MHz

Input Clock Duty Cycle

40

60

%



15

µs

NOTES:

1. The PLL will track a spread spectrum clock input.

2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. To be used only for low speed system debug.

3. Will lock to input frequency as low as 30MHz at room temperature and nominal or higher supply voltage (1.8V - 1.9V).

4. Application clock frequency is the range over which timing specifications apply.

5. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the

stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic LOW state, enters

the power-down mode, and later return to active operation. CLK and CLK may be left floating after they have been driven LOW for one complete clock cycle.

Symbol

Description

Test Conditions

Min.

Max.

Unit

LOW to HIGH Level Propagation Delay Time

TBD

ns

CLK to any output

HIGH to LOW Level Propagation Delay Time

TBD

ns

CLK to any output

Jitter(cycle-to-cycle)

166/200/266MHz

0

40

ps

0

-40

Jitter(period)

166/200/266MHz

-40

40

ps

Half-PeriodJitter

166/200/266MHz

-60

60

ps

OutputClockSlewRate(single-ended)

166/200/266MHz (20% to 80%)

1.5

2.5

3

V/ns

OutputEnable(OE)

0.5



V/ns

Input Clock Slew Rate

1

2.5

4

StaticPhaseOffset

166/200/266MHz

-50

50

ps

DynamicPhaseOffset

166/200/266MHz

-50

50

ps

Output Skew

40

ps

Output Enable to any Y or Y

8ns

Output Disable to any Y or Y

8ns

ACDifferentialOutputCrosspointVoltage

Differentialoutputsterminatedwith120

Ω

V

ACDifferentialInputVoltage

0.6

V

ACDifferentialInputCrosspointVoltage

V

The PLL on the CSPU877D will meet all the above test parameters while supporting SSC synthesizers with the following parameters:

SSC

ModulationFrequency

30



33

KHz

SSC

ClockInputFrequencyDeviation

0



-0.5

%

PLLLoopBandwidth

2

MHz

NOTES:

1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage

only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50

Ω equal length cables with SMA connectors

on the test board.

2. Refers to transition of non-inverting output.

3. Period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other.

4. To eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (CLK, CLK) and feedback clock input (FBIN, FBIN) are recommended

to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these nominal values is not mandatory if it can be adequately demonstrated

that alternative characteristics meet the requirements of the registered DDR2 DIMM application.

5. Static phase offset does not include jitter.