IDTCSPU877D datasheet(1/13 Pages) IDT | 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

1 page

IDTCSPU877D

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

COMMERCIALTEMPERATURERANGE

FBOUT

FBIN

PLL

CLK

POWER

DOWN

AND

TEST

MODE

LOGIC

AVDD

LD or OE

LD, OS, or OE

PLL BYPASS

10K

Ω - 100KΩ

2004

Integrated Device Technology, Inc.

DSC 6575/4

IDTCSPU877D

COMMERCIAL TEMPERATURE RANGE

1.8V PHASE LOCKED LOOP

DIFFERENTIAL 1:10 SDRAM

CLOCK DRIVER

AUGUST 2004

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• 1 to 10 differential clock distribution

• Optimized for clock distribution in DDR2 (Double Data Rate)

SDRAM applications

• Operating frequency: 125MHz to 340MHz

• Very low skew:

≤≤≤≤≤40ps

• Very low jitter:

≤≤≤≤≤40ps

• 1.8V AVDD and 1.8V VDDQ

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Available in 52-Ball VFBGA and 40-pin MLF packages

FUNCTIONAL BLOCK DIAGRAM

NOTE:

The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.

DESCRIPTION:

TheCSPU877DisaPLLbasedclockdriverthatactsasazerodelaybuffer

to distribute one differential clock input pair(CLK, CLK ) to 10 differential

output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output

(FBOUT,FBOUT). Externalfeedbackpins(FBIN,FBIN)forsynchronization

oftheoutputstotheinputreferenceisprovided.OE,OS,andAVDDcontrolthe

power-down and test mode logic. When AVDD is grounded, the PLL is turned

off and bypassed for test mode purposes. When the differential clock inputs

(CLK,CLK)arebothatlogiclow,thisdevicewillenteralowpower-downmode.

In this mode, the receivers are disabled, the PLL is turned off, and the output

clockdriversaredisabled,resultinginacurrentconsumptiondeviceoflessthan

500

µA.

TheCSPU877Drequiresnoexternalcomponentsandhasbeenoptimised

forverylowphaseerror,skew,andjitter,whilemaintainingfrequencyandduty

cycle over the operating voltage and temperature range. The CSPU877D,

designedforuseinbothmoduleassembliesandsystemmotherboardbased

solutions,providesanoptimumhigh-performanceclocksource.

The CSPU877D is available in Commercial Temperature Range (0°C to

+70°C). See Ordering Information for details.

APPLICATIONS:

• Meets or exceeds JEDEC standard 82.8 for registered DDR2

clock driver

• Along with SSTU32864/65/66, DDR2 register, provides complete

solution for DDR2 DIMMs

Part Number	Components Description	Html View	Manufacturer
IDTCSPUA877A	1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER	1 2 3 4 5 More	Integrated Device Technology
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TLC2933A	HIGH PERFORMANCE PHASE LOCKED LOOP	1 2 3 4 5 More	Texas Instruments
NB7L111M	2.5V / 3.3V 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output	1 2 3 4 5 More	ON Semiconductor
MC100LVE111_06	3.3V ECL 1:9 Differential Clock Driver	1 2 3 4 5 More	ON Semiconductor
AZ100LVE310	ECL/PECL 2:8 Differential Clock Driver	1 2 3 4 5	Arizona Microtek, Inc
NBSG111	2.5V/3.3V SiGe Differential 1:10 Clock/Data Driver with RSECL Outputs	1 2 3 4 5 More	ON Semiconductor

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