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P4C163-45JCLF Datasheet(PDF) 4 Page - Pyramid Semiconductor Corporation |
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P4C163-45JCLF Datasheet(HTML) 4 Page - Pyramid Semiconductor Corporation |
4 / 12 page P4C163/163L Page 4 of 12 Document # SRAM120 REV C Symbol Parameter Unit -25 -35 -45 Min Max Min Max Min Max t RC Read Cycle Time 25 35 45 ns t AA Address Access Time 25 35 45 ns t AC Chip Enable 25 35 45 ns Access Time t OH Output Hold from 3 3 3 ns Address Change t LZ Chip Enable to 3 3 3 ns Output in Low Z t HZ Chip Disable to 10 15 20 ns Output in High Z t OE Output Enable 13 18 20 ns Low to Data Valid t OLZ Output Enable 3 3 3 ns Low to Low Z t OHZ Output Enable 12 15 20 ns High to High Z t PU Chip Enable to 0 0 0 ns Power Up Time t PD Chip Disable to 20 20 25 ns Power Down Time AC ELECTRICAL CHARACTERISTICS—READ CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) READ CYCLE NO. 1 (OE OE OE OE OE CONTROLLED)(5) Notes: 5. WE is HIGH for READ cycle. 6. CE 1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE 1 transition LOW and CE 2 transition HIGH. 8. Transition is measured ± 200mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. |
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