CY7C1021CV33
Document #: 38-05132 Rev. *G
Page 6 of 13
Switching Characteristics Over the Operating Range[7]
Parameter
Description
-8
-10
-12
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tpower
[8]
VCC(typical) to the first access
100
100
100
100
µs
tRC
Read Cycle Time
8
10
12
15
ns
tAA
Address to Data Valid
8
10
12
15
ns
tOHA
Data Hold from Address Change
3
3
3
3
ns
tACE
CE LOW to Data Valid
8
10
12
15
ns
tDOE
OE LOW to Data Valid
5
5
6
7
ns
tLZOE
OE LOW to Low-Z[9]
00
0
0
ns
tHZOE
OE HIGH to High-Z[9, 10]
45
6
7
ns
tLZCE
CE LOW to Low-Z[9]
33
3
3
ns
tHZCE
CE HIGH to High-Z[9, 10]
45
6
7
ns
tPU
[11]
CE LOW to Power-Up
0
0
0
0
ns
tPD
[11]
CE HIGH to Power-Down
8
10
12
15
ns
tDBE
Byte Enable to Data Valid
5
5
6
7
ns
tLZBE
Byte Enable to Low-Z
0
0
0
0
ns
tHZBE
Byte Disable to High-Z
4
5
6
7
ns
Write Cycle[12]
tWC
Write Cycle Time
8
10
12
15
ns
tSCE
CE LOW to Write End
7
8
9
10
ns
tAW
Address Set-up to Write End
7
8
9
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
10
ns
tSD
Data Set-up to Write End
5
5
6
8
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low-Z[9]
33
3
3
ns
tHZWE
WE LOW to High-Z[9, 10]
45
6
7
ns
tBW
Byte Enable to End of Write
6
7
8
9
ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state
voltage.
11. This parameter is guaranteed by design and is not tested.
12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a
Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal
that terminates the Write.
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
