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IDT82P2828BHG Datasheet(PDF) 9 Page - Integrated Device Technology

Part # IDT82P2828BHG
Description  28(1) Channel High-Density T1/E1/J1 Line Interface Unit
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT82P2828BHG Datasheet(HTML) 9 Page - Integrated Device Technology

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IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
List of Figures
9
January 11, 2007
Figure-49 1+1 HPS Scheme, E1 75 ohm Single-Ended Interface (Shared Common Transformer) ........................................................................... 74
Figure-50 JTAG Architecture ..................................................................................................................................................................................... 121
Figure-51 JTAG State Diagram ................................................................................................................................................................................. 122
Figure-52 Transmit Clock Timing Diagram ................................................................................................................................................................ 134
Figure-53 Receive Clock Timing Diagram ................................................................................................................................................................. 134
Figure-54 CLKE1 Clock Timing Diagram ................................................................................................................................................................... 135
Figure-55 E1 Jitter Tolerance Performance ............................................................................................................................................................... 137
Figure-56 T1/J1 Jitter Tolerance Performance .......................................................................................................................................................... 137
Figure-57 E1 Jitter Transfer Performance ................................................................................................................................................................. 138
Figure-58 T1/J1 Jitter Transfer Performance ............................................................................................................................................................. 138
Figure-59 Read Operation in Serial Microprocessor Interface .................................................................................................................................. 139
Figure-60 Write Operation in Serial Microprocessor Interface ................................................................................................................................... 139
Figure-61 Timing Diagram ......................................................................................................................................................................................... 140
Figure-62 Parallel Motorola Non-Multiplexed Microprocessor Interface Read Cycle ................................................................................................ 141
Figure-63 Parallel Motorola Non-Multiplexed Microprocessor Interface Write Cycle ................................................................................................ 142
Figure-64 Parallel Intel Non-Multiplexed Microprocessor Interface Read Cycle ....................................................................................................... 143
Figure-65 Parallel Intel Non-Multiplexed Microprocessor Interface Write Cycle ........................................................................................................ 144
Figure-66 Parallel Motorola Multiplexed Microprocessor Interface Read Cycle ........................................................................................................ 145
Figure-67 Parallel Motorola Multiplexed Microprocessor Interface Write Cycle ........................................................................................................ 146
Figure-68 Parallel Intel Multiplexed Microprocessor Interface Read Cycle ............................................................................................................... 147
Figure-69 Parallel Intel Multiplexed Microprocessor Interface Write Cycle ............................................................................................................... 148
Figure-70 JTAG Timing ............................................................................................................................................................................................. 149


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