4-Mbit (256K x 16) Static RAM
CY7C1041CV33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05134 Rev. *H
Revised September 1, 2006
Features
• Pin equivalent to CY7C1041BV33
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
•High speed
—tAA = 10 ns
• Low active power
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free and non Pb-free 44-pin 400-mil-
SOJ, 44-pin TSOP II and 48-ball FBGA packages
Functional Description[1]
The CY7C1041CV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable
(BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written
into the location specified on the address pins (A0–A17). If Byte
HIGH Enable (BHE) is LOW, then data from I/O pins
(I/O8–I/O15) is written into the location specified on the
address pins (A0–A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The
input/output
pins
(I/O0–I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1041CV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Notes:
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.
Logic Block Diagram
Pin Configuration
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
256K × 16
ARRAY
A0
I/O0–I/O7
OE
I/O8–I/O15
CE
WE
BLE
BHE
Top View
SOJ/
TSOP II
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
VCC
A5
A6
A7
A8
A0
A1
OE
VSS
A17
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
A3
A4
18
17
20
19
I/O3
27
28
25
26
22
21
23
24
VSS
I/O6
I/O4
I/O5
I/O7
A16
A15
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A14
A13
A12
A11
A9
A10
NC
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