CY7C1141V18
CY7C1156V18
CY7C1143V18
CY7C1145V18
Document Number: 001-06583 Rev. *C
Page 6 of 28
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1141V18
−D[7:0]
CY7C1156V18
−D[8:0]
CY7C1143V18
−D[17:0]
CY7C1145V18
−D[35:0]
WPS
Input-
Synchronous
Write Port Select
− Active LOW. Sampled on the rising edge of the K clock. When asserted active,
a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes
D[x:0] to be ignored.
NWS0, NWS1,
Input-
Synchronous
Nibble Write Select 0, 1
− Active LOW.(CY7C1141V18 Only) Sampled on the rising edge of the K
and K clocks during write operations. This is used to select the nibble that is written into the device
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write
Select causes the corresponding nibble of data to be ignored and not written into the device.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
− Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. This is used to select the byte that is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1156V18
− BWS0 controls D[8:0]
CY7C1143V18
− BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1145V18
− BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
causes the corresponding byte of data to be ignored and not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1141V18, 2M x 9 (4 arrays each of 512K
x 9) for CY7C1156V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1143V18, and 512K x 36 (4
arrays each of 128K x 36) for CY7C1145V18. Therefore, only 19 address inputs are needed to access
the entire memory array of CY7C1141V18 and CY7C1156V18, 18 address inputs for CY7C1143V18
and 17 address inputs for CY7C1145V18. These inputs are ignored when the appropriate port is
deselected.
Q[x:0]
Outputs-
Synchronous
Data Output signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the K and K clocks during read operations or K and K when in
single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1141V18
−Q[7:0]
CY7C1156V18
−Q[8:0]
CY7C1143V18
−Q[17:0]
CY7C1145V18
−Q[35:0]
RPS
Input-
Synchronous
Read Port Select
− Active LOW. Sampled on the rising edge of Positive Input Clock (K). When
active, a read operation is initiated. Deasserting causes the read port to be deselected. When
deselected, the pending access is enabled to complete and the output drivers are automatically
tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four
sequential transfers.
QVLD
Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ.
K
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs presented to the device and
to drive out data through Q[x:0] when in single clock mode.
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”
on page 23.
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