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CY7C1150V18-333BZC Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C1150V18-333BZC
Description  18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1150V18-333BZC Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C1146V18
CY7C1157V18
CY7C1148V18
CY7C1150V18
Document Number: 001-06621 Rev. *C
Page 7 of 27
DOFF
Input
DLL Turn Off
− Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operation are different from those listed in this data sheet. For normal
operation, connect this pin to a pull up through a 10 K
Ω or less pull up resistor. The device behaves
in DDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to
167 MHz with DDR-I timing.
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Tie to any voltage level.
NC/36M
N/A
Not connected to the die. Tie to any voltage level.
NC/72M
N/A
Not connected to the die. Tie to any voltage level.
NC/144M
N/A
Not connected to the die. Tie to any voltage level.
NC/288M
N/A
Not connected to the die. Tie to any voltage level.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and
AC measurement points.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name
IO
Pin Description


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