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CY7C1266V18-400BZC Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7C1266V18-400BZC
Description  36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1266V18-400BZC Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY7C1266V18
CY7C1277V18
CY7C1268V18
CY7C1270V18
Document Number: 001-06347 Rev. *C
Page 6 of 27
Pin Definitions
Pin Name
IO
Pin Description
DQ[x:0]
Input/Output-
Synchronous
Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during
valid write operations. These pins drive out the requested data during a read operation. Valid
data is driven out on the rising edge of both the K and K clocks during read operations. When
read access is deselected, Q[x:0] are automatically tri-stated.
CY7C1266V18 – DQ[7:0]
CY7C1277V18 – DQ[8:0]
CY7C1268V18 – DQ[17:0]
CY7C1270V18 – DQ[35:0]
LD
Input-
Synchronous
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when
a bus cycle sequence is to be defined. This definition includes address and read/write direction.
All transactions operate on a burst of 2 data. LD must meet the setup and hold times around
edge of K.
NWS0, NWS1
Input-
Synchronous
Nibble Write Select 0, 1, Active LOW (CY7C1266V18 only). Sampled on the rising edge of
the K and K clocks during write operations. Used to select which nibble is written into the device
during the current portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select causes the corresponding nibble of data to be ignored and not written into the
device.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1277V18
− BWS0 controls D[8:0]
CY7C1268V18
− BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1270V18
− BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select causes the corresponding byte of data to be ignored and not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write opera-
tions. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1266V18, 4M x 9 (2 arrays
each of 2M x 9) for CY7C1277V18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1268V18, and
1M x 36 (2 arrays each of 512K x 36) for CY7C1270V18.
R/W
Input-
Synchronous
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up
and hold times around edge of K.
QVLD
Valid Output
Indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ
and CQ.
K
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous data being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
CQ
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Character-
istics” on page 22.
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