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P4C149-12LSM Datasheet(PDF) 4 Page - Pyramid Semiconductor Corporation |
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P4C149-12LSM Datasheet(HTML) 4 Page - Pyramid Semiconductor Corporation |
4 / 10 page P4C148/P4C149 Page 4 of 10 Document # SRAM104 REV B TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE WE WE WE WE CONTROLLED)(9) Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE high, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CE CE CE CE/CS CS CS CS CS CONTROLLED)(9) AC CHARACTERISTICS—WRITE CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time 10 12 15 20 25 35 45 55 tCW Chip Enable Time to End of Write 8 10 12 16 20 25 30 35 tAW Address Valid to End of Write 8 10 12 16 20 25 30 35 tAS Address Set-up Time 00000 000 tWP Write Pulse Width 8 10 12 16 20 25 30 35 tAH Address Hold Time from End of Write 00000 000 tDW Data Valid to End of Write 5679 12 16 20 25 tDH Data Hold Time 00000 000 tWZ Write Enable to Output in High Z 56778 12 15 20 tOW Output Active from End of Write 00000 000 Sym Parameter -10 -12 -45 -55 -15 -20 -25 -35 |
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