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P4C187-25JC Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation |
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P4C187-25JC Datasheet(HTML) 6 Page - Pyramid Semiconductor Corporation |
6 / 12 page P4C187/187L Page 6 of 12 Document # SRAM111 REV B TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CE CE CE CE CONTROLLED)(9) Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Due to the ultra-high speed of the P4C187/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 Ω test environment should be terminated into a 50 Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 Ω resistor must be used in series with D OUT to match 166Ω (Thevenin Resistance). AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Mode CE CE CE CE CE WE WE WE WE WE Output Power Standby H X High Z Standby Read L H D OUT Active Write L L High Z Active |
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