CY7C1241V18
CY7C1256V18
CY7C1243V18
CY7C1245V18
Document Number: 001-06365 Rev. *C
Page 9 of 28
on the rising edge of the Positive Input Clock only (K). Each
port select input can deselect the specified port. Deselecting
a port does not affect the other port. All pending transactions
(read and write) are completed before the device is
deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to enable the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175
Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data
capture on high speed systems. Two echo clocks are
generated by the QDR-II+. CQ is referenced with respect to K
and CQ is referenced with respect to K. These are free running
clocks and are synchronized to the input clock of the QDR-II+.
The timing for the echo clocks is shown in “Switching Charac-
teristics” on page 23.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on
high speed systems. The QVLD is generated by the QDR-II+
device along with data output. This signal is also edge-aligned
with the echo clock and follows the timing of any data pin. This
signal is asserted half a cycle before valid data arrives.
Delay Lock Loop (DLL)
These chips use a DLL that is designed to function between
120 MHz and the specified maximum clock frequency. The
DLL may be disabled by applying ground to the DOFF pin.
When the DLL is turned off, the device behaves in QDR-I
mode (with 1.0 cycle latency and a longer access time). For
more information, refer to the application note, DLL Consider-
ations in QDRII/DDRII/QDRII+/DDRII+. The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary for the DLL to
be reset to lock to the desired frequency. During power up,
when the DOFF is tied HIGH, the DLL is locked after 2048
cycles of stable clock.
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