IDT82V2051E datasheet(4/61 Pages) IDT

Part #	IDT82V2051E

Description	SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

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Manufacturer	IDT [Integrated Device Technology]

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4 / 61 page

IDT82V2051E

SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

Table of Contents

4

December 9, 2005

3.8.1 Definition Of Line Coding Error ............................................................................... 27

3.8.2 Error Detection And Counting ................................................................................. 27

3.8.3 Bipolar Violation And PRBS Error Insertion ............................................................ 28

3.9

Line Driver Failure Monitoring ........................................................................................... 28

3.10 MCLK And TCLK ..............................................................................................................29

3.10.1 Master Clock (MCLK).............................................................................................. 29

3.10.2 Transmit Clock (TCLK) ........................................................................................... 29

3.11 Microcontroller Interfaces .................................................................................................30

3.11.1 Parallel Microcontroller Interface ............................................................................ 30

3.11.2 Serial Microcontroller Interface ............................................................................... 30

3.12 Interrupt Handling ............................................................................................................. 30

3.13 5V Tolerant I/O Pins ......................................................................................................... 31

3.14 Reset Operation ................................................................................................................ 31

3.15 Power Supply .................................................................................................................... 31

4

Programming Information ........................................................................................................ 32

4.1

Register List And Map ...................................................................................................... 32

4.2

Reserved Registers ..........................................................................................................32

4.3

Register Description ......................................................................................................... 33

4.3.1 Control Registers .................................................................................................... 33

4.3.2 Transmit Path Control Registers............................................................................. 35

4.3.3 Receive Path Control Registers.............................................................................. 37

4.3.4 Network Diagnostics Control Registers .................................................................. 39

4.3.5 Interrupt Control Registers...................................................................................... 41

4.3.6 Line Status Registers.............................................................................................. 43

4.3.7 Interrupt Status Registers ....................................................................................... 45

4.3.8 Counter Registers ................................................................................................... 46

5

Hardware Control Pin Summary .............................................................................................. 47

6

Test Specifications .................................................................................................................... 49

7

Microcontroller Interface Timing Characteristics ................................................................... 56

7.1

Serial Interface Timing ...................................................................................................... 56

7.2

Parallel Interface Timing ...................................................................................................57

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