IDT82V2051E datasheet(5/61 Pages) IDT

Part #	IDT82V2051E

Description	SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

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Manufacturer	IDT [Integrated Device Technology]

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List of Tables

5

December 9, 2005

Table-1

Pin Description ................................................................................................................ 9

Table-2

Transmit Waveform Value For E1 75 ohm.................................................................... 16

Table-3

Transmit Waveform Value For E1 120 ohm.................................................................. 16

Table-4

Impedance Matching for Transmitter ............................................................................ 17

Table-5

Impedance Matching for Receiver ................................................................................ 18

Table-6

Criteria of Starting Speed Adjustment........................................................................... 22

Table-7

LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 22

Table-8

LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 23

Table-9

AIS Condition ................................................................................................................ 23

Table-10

Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 24

Table-11

EXZ Definition ............................................................................................................... 27

Table-12

Interrupt Event............................................................................................................... 31

Table-13

Register List and Map ................................................................................................... 32

Table-14

ID: Device Revision Register ........................................................................................ 33

Table-15

RST: Reset Register ..................................................................................................... 33

Table-16

GCF: Global Configuration Register ............................................................................. 33

Table-17

TERM: Transmit and Receive Termination Configuration Register .............................. 33

Table-18

JACF: Jitter Attenuation Configuration Register ........................................................... 34

Table-19

TCF0: Transmitter Configuration Register 0 ................................................................. 35

Table-20

TCF1: Transmitter Configuration Register 1 ................................................................. 35

Table-21

TCF2: Transmitter Configuration Register 2 ................................................................. 35

Table-22

TCF3: Transmitter Configuration Register 3 ................................................................. 36

Table-23

TCF4: Transmitter Configuration Register 4 ................................................................. 36

Table-24

RCF0: Receiver Configuration Register 0..................................................................... 37

Table-25

RCF1: Receiver Configuration Register 1..................................................................... 37

Table-26

RCF2: Receiver Configuration Register 2..................................................................... 38

Table-27

MAINT0: Maintenance Function Control Register 0...................................................... 39

Table-28

MAINT1: Maintenance Function Control Register 1...................................................... 39

Table-29

MAINT6: Maintenance Function Control Register 6...................................................... 39

Table-30

INTM0: Interrupt Mask Register 0 ................................................................................. 41

Table-31

INTM1: Interrupt Masked Register 1 ............................................................................. 41

Table-32

INTES: Interrupt Trigger Edge Select Register ............................................................. 42

Table-33

STAT0: Line Status Register 0 (real time status monitor)............................................. 43

Table-34

STAT1: Line Status Register 1 (real time status monitor)............................................. 44

Table-35

INTS0: Interrupt Status Register 0 ................................................................................ 45

Table-36

INTS1: Interrupt Status Register 1 ................................................................................ 45

Table-37

CNT0: Error Counter L-byte Register 0......................................................................... 46

Table-38

CNT1: Error Counter H-byte Register 1 ........................................................................ 46

Table-39

Hardware Control Pin Summary ................................................................................... 47

Table-40

Absolute Maximum Rating ............................................................................................ 49

Table-41

Recommended Operation Conditions ........................................................................... 49

List of Tables

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