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P4C188-20LC Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C188-20LC Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
1 / 12 page 1 Document # SRAM112 REV A Revised October 2005 DESCRIPTION The P4C188 and P4C188L are 65,536-bit ultra high speed static RAMs organized as 16K x 4. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAMs operate from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Single 5V±10% Power Supply Data Retention with 2.0V Supply (P4C188L Military) Three-State Outputs TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 22-Pin 300 mil DIP – 24-Pin 300 mil SOJ – 22-Pin 290 x 490 mil LCC FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 (Industrial) – 15/20/25/35/45 ns (Military) Low Power (Commercial/Military) – 715 mW Active – 12/15 – 550/660 mW Active – 20/25/35/45 – 193/220 mW Standby (TTL Input) – 83/110 mW Standby (CMOS Input) P4C188 – 15 mW Standby (CMOS Input) (P4C188L Military) FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS P4C188/P4C188L ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS DIP (P3, D3, C3) LCC (L3) For SOJ pin configuration, please see end of datasheet. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption to a low 715mW active, 193mW standby and only 5mW in the P4C188L version. The P4C188 and P4C188L are available in 22-pin 300 mil DIP, 24-pin 300 mil SOJ and 22-pin LCC packages provid- ing excellent board level densities. |
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Similar Description - P4C188-20LC |
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