PRELIMINARY
18-Mbit QDR-II™ SRAM 2-Word
Burst Architecture
CY7C1310CV18
CY7C1910CV18
CY7C1312CV18
CY7C1314CV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 001-07164 Rev. *B
Revised September 20, 2006
Features
• Separate Independent Read and Write data ports
— Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• QDR-II operates with 1.5 cycle read latency when the
DLL is enabled
• Operates like a QDR-I device with 1 cycle read latency
in DLL off mode
• Available in x 8, x 9, x 18, and x 36 configurations
• Full data coherency, providing most current data
•Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both lead-free and non-lead free packages
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310CV18 – 2M x 8
CY7C1910CV18 – 2M x 9
CY7C1312CV18 – 1M x 18
CY7C1314CV18 – 512K x 36
Functional Description
The CY7C1310CV18, CY7C1910CV18, CY7C1312CV18 and
CY7C1314CV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of the K clock. Accesses to the QDR-II Read
and Write ports are completely independent of one another. In
order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (DDR) interfaces. Each
address
location
is
associated
with
two
8-bit
words
(CY7C1310CV18) or 9-bit words (CY7C1910CV18) or 18-bit
words (CY7C1312CV18) or 36-bit words (CY7C1314CV18)
that burst sequentially into or out of the device. Since data can
be transferred into and out of the device on every rising edge
of both input clocks (K and K and C and C), memory bandwidth
is maximized while simplifying system design by eliminating
bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
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