P4C1026-15L32I datasheet(4/10 Pages) PYRAMID

Part #	P4C1026-15L32I

Description	ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM

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Manufacturer	PYRAMID [Pyramid Semiconductor Corporation]

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P4C1026

Page 4 of 10

Document # SRAM127 REV E

TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)

Notes:

1. Stresses greater than those listed under MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification

is not implied. Exposure to MAXIMUM rating conditions for extended

periods may affect reliability.

2. Extended temperature operation guaranteed with 400 linear feet per

minute of air flow.

3. Transient inputs with V

IL and IIL not more negative than –3.0V and

–100mA, respectively, are permissible for pulse widths up to 20 ns.

4. This parameter is sampled and not 100% tested.

5. WE is HIGH for READ cycle.

6. CE is LOW and OE is LOW for READ cycle.

7. ADDRESS must be valid prior to, or coincident with CE transition LOW.

8. Transition is measured ± 200 mV from steady state voltage prior to

change, with loading as specified in Figure 1. This parameter is

sampled and not 100% tested.

9. Read Cycle Time is measured from the last valid address to the first

transitioning address.

TIMING WAVEFORM OF READ CYCLE NO. 1 (OE

OE

OE CONTROLLED)(5)

AC CHARACTERISTICS—READ CYCLE

(V

CC = 5V ± 10%, All Temperature Ranges)

(2)

Sym.

t

RC

t

AA

t

AC

t

OH

t

LZ

t

HZ

t

PU

t

PD

Parameter

Read Cycle Time

Address Access Time

Chip Enable Access Time

Output Hold from Address Change

Chip Enable to Output in Low Z

Chip Disable to Output in High Z

Chip Enable to Power Up Time

Chip Disable to Power Down Time

-15

Min

15

2

0

Max

15

8

15

-20

Min

20

2

3

0

Max

20

9

20

-25

Min

25

2

3

0

Max

25

10

25

-35

Min

35

2

3

0

Max

35

11

35

Unit

ns

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