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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document Number: 38-05620 Rev. *C
Page 3 of 28
Logic Block Diagram (CY7C1313BV18)
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
18
72
18
BWS[1:0]
VREF
Write
Reg
36
A(17:0)
18
C
C
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
Logic Block Diagram (CY7C1315BV18)
CLK
A(16:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
17
36
144
36
BWS[3:0]
VREF
Write
Reg
72
A(16:0)
17
C
C
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
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