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PRELIMINARY
CY7C1310CV18
CY7C1910CV18
CY7C1312CV18
CY7C1314CV18
Document #: 001-07164 Rev. *B
Page 3 of 26
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
250
200
167
MHz
Maximum Operating Current
600
550
500
mA
Logic Block Diagram (CY7C1312CV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
18
36
18
BWS[1:0]
VREF
18
A(18:0)
19
C
C
18
Write
Reg
Write
Reg
CQ
CQ
18
DOFF
Logic Block Diagram (CY7C1314CV18)
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
36
72
36
BWS[3:0]
VREF
36
A(17:0)
18
C
C
36
Write
Reg
Write
Reg
CQ
CQ
36
DOFF
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