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CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. *E
Page 3 of 28
Logic Block Diagram (CY7C1312BV18)
Logic Block Diagram (CY7C1314BV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
36
18
BWS[1:0]
VREF
18
A(18:0)
19
18
CQ
CQ
DOFF
Q[17:0]
18
QVLD
18
Write
Reg
Write
Reg
C
C
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
72
36
BWS[3:0]
VREF
36
A(17:0)
18
36
CQ
CQ
DOFF
Q[35:0]
36
QVLD
36
Write
Reg
Write
Reg
C
C