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IDT70121S45JG Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70121S45JG Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 15 page ©2006 Integrated Device Technology, Inc. APRIL 2006 DSC 2654/10 1 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT LOGIC Address Decoder I/O Control R/ WL CEL OEL BUSYL A10L A0L 2654 drw 01 I/O0L-I/O8L CEL OEL R/ WL INTL BUSYR I/O0R-I/O8R A10R A0R INTR CER OER (2) (1,2) (1,2) (2) R/ WR CER OER R/ WR 11 11 HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT IDT70121S/L IDT70125S/L NOTES: 1. 70121 (MASTER): BUSY is non-tri-stated push-pull output. 70125 (SLAVE): BUSY is input. 2. INT is non-tri-stated push-pull output. Functional Block Diagram Features ✵ High-speed access – Commercial: 25/35/45/55ns (max.) – Industrial: 35ns (max.) ◆ Low-power operation – IDT70121/70125S Active: 675mW (typ.) Standby: 5mW (typ.) – IDT70121/70125L Active: 675mW (typ.) Standby: 1mW (typ.) ◆ Fully asychronous operation from either port ◆ ◆ ◆ ◆ ◆ MASTER IDT70121 easily expands data bus width to 18 bits or more using SLAVE IDT70125 chip ◆ On-chip port arbitration logic (IDT70121 only) ◆ BUSY output flag on Master; BUSY input on Slave ◆ INT flag for port-to-port communication ◆ Battery backup operation—2V data retention ◆ TTL-compatible, signal 5V (±10%) power supply ◆ Available in 52-pin PLCC ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information |
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