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P4C168-12FSM Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation |
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P4C168-12FSM Datasheet(HTML) 6 Page - Pyramid Semiconductor Corporation |
6 / 15 page P4C168, P4C169, P4C170 Page 6 of 15 Document # SRAM107 REV A Mode CE CE CE CE CE (CS CS CS CS CS) WE WE WE WE WE Output Standby (Deselect) H X High Z Read L H D OUT Write L L High Z TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CE CE CE CE/CS CS CS CS CS CONTROLLED)(10) TRUTH TABLES P4C168 (P4C169) P4C170 Mode CE CE CE CE CE WE WE WE WE WE OE OE OE OE OE Output Deselect H X X High Z Read L H L D OUT Output Inhibit L H H High Z Write L L X High Z Notes: 10. CE/CS and WE must be LOW for WRITE cycle. 11. If CE/CS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 12. Write Cycle Time is measured from the last valid address to the first transitioning address. TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE WE WE WE WE CONTROLLED)(10) |
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