CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. *E
Page 9 of 28
QDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock (C/C) of the QDR-II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timings for the echo clocks are shown in
the Switching Characteristics.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 80 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K for
a minimum of 30 ns. However, it is not necessary to specifically
reset the DLL set to lock the DLL to the desired frequency. The
DLL automatically locks 1024 clock cycles after a stable clock is
presented. The DLL may be disabled by applying ground to the
DOFF pin. For information refer to the application note ‘DLL
Considerations in QDRII/DDRII/QDRII+/DDRII+’.
Application Example
Figure 1 shows the use of QDR-II in an application.
Figure 1. Application Example
Vt = Vddq/2
CC#
D
A
K
CC#
D
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM #1
SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
R = 50
οηµσ
R = 250
οηµσ
R = 250
οηµσ
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#
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