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P4C187-15JM Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C187-15JM Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
1 / 12 page 1 Document # SRAM111 REV B Revised April 2007 FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35/45 ns (Commercial) – 12/15/20/25/35 /45 ns (Industrial) – 15/20/25/35/45/55/70/85 ns (Military) Low Power Operation – 743 mW Active -10 – 660/770 mW Active for -12/15 – 550/660 mW Active for -20/25/35 – 193/220 mW Standby (TTL Input) – 83/110 mW Standby (CMOS Input) P4C187 – 5.5 mW Standby (CMOS Input) P4C187L (Military) Single 5V±10% Power Supply P4C187/P4C187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM DIP (P3, D3, C3) LCC Pin configurations at end of datasheet. Data Retention with 2.0V Supply (P4C187L Military) Separate Data I/O Three-State Output TTL Compatible Output Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 22-Pin 300 mil DIP – 24-Pin 300 mil SOJ – 22-Pin 290x490 mil LCC – 28-Pin 350x550 mil LCC DESCRIPTION The P4C187/P4C187L are 65, 536-bit ultra high speed static RAMs organized as 64K x 1. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10% tolerancepowersupply.Dataintegrityismaintainedforsup- ply voltages down to 2.0V, typically drawing 10µA. Access times as fast as 10 nanoseconds are available, greatly enhancing system speeds. CMOS reduces power consumption to a low 743mW active, 193/83mW standby for TTL/CMOS inputs and only 5.5 mW standby for the P4C187L. TheP4C187/P4C187Lareavailablein22-pin300milDIP, 24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro- viding excellent board level densities. 1 SOJ (J4) |
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